The present invention relates generally to information processing systems and more particularly to an improved information transfer system in a computer related environment.
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term xe2x80x9cbandwidthxe2x80x9d is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in xe2x80x9choldingxe2x80x9d buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or xe2x80x9cPCIxe2x80x9d system bridge circuit buffers are assigned to PCI devices, which are installed in PCI xe2x80x9cslotsxe2x80x9d and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted into PCI xe2x80x9cslotsxe2x80x9d, i.e. into board connector terminals mounted on a system motherboard.
Standard PCI-PCI bridges are utilized in the industry today as a means to provide added slots for PCI devices since individual PCI busses are limited to 10 loads per bus at 33 MHz and 5 loads at 66 MHz (a soldered device counts as one load and a slotted device counts as two loads). This requires a combination of multiple PCI host bridges and/or multiple standard PCI-PCI bridges per each server drawer where server drawers typically house 14-16 PCI slots per drawer. The total integrated circuit (IC) or chip and packaging cost is expensive utilizing standard components.
Thus, there is an increasing need for an improved computer system which is designed to be able to efficiently handle greater numbers of peripheral adapters in computer systems.
A method and implementing system is provided in which multiple PCI busses are managed through a combination multiple node PCI-to-PCI bridge including a non-blocking PCI Router (PCIR) circuit. Bridge buffer re-order rules are defined to establish when buffers are re-ordered such that subsequent transactions are allowed to be attempted ahead of transactions already present in the buffer at a particular node. Other buffer management and transaction ordering rules are defined to meet PCI ordering requirements and also to allow peer-to-peer and I/O Processor (IOP) traffic between multiple secondary nodes in a non-blocking manner.